Последовательный процессор алгоритма шифрования AES на базе FPGA

Abstract

This article describes the design of the AES-128 encryption and decryption algorithm processor. The design is written in VHDL and is implemented in such FPGA chips as Xilinx Virtex 5,6,7 and Spartan 6. The goal of the work was to build an iterative AES IP-core that is optimized for maximum encryption and decryption bandwidth. Several different designs were implemented and compared. The best designs were able to perform on a par with the best commercial and opensource solutions that are openly available. Thorough analysis of different AES-processor structures described in the work can be of use for the designs with various optimization criteria